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Table 141. REGISTER 0xCD  Push Trange (PowerOn Default = 0x0C)
Bit
Name
R/W
Description
<3:0>
RNG
R/W
These bits determine the PWM duty cycle vs. the temperature range for automatic fan control.
0000 = 2癈
0001 = 2.5癈
0010 = 3.33癈
0011 = 4癈
0100 = 5癈
0101 = 6.67癈
0110 = 8癈
0111 = 10癈
1000 = 13.33癈
1001 = 16癈
1010 = 20癈
1011 = 26.67癈
1100 = 32癈 (default)
1101 = 40癈
1110 = 53.33癈
1111 = 80癈
<7:4>
Reserved
Table 142. PUSH TEMPERATURE LIMIT REGISTERS
Register Address
R/W
Description
PowerOn Default
0xCE
R/W
Push High Limit
0x7F
0xCF
R/W
Push Low Limit
0x81
0xD0
R/W
Push THERM Limit
0x64
Table 143. GENERIC PECI INTERFACE BLOCK
Register Address
R/W
Description
Default
0xD1
R/W
Generic PECI CPU Address. This sets the target processor address for the
PECI command
0x00
0xD2
R/W
Write Length. This sets the number of byte transferred to the target device
when the command is executed
0x00
0xD3
R/W
Read Length. This specifies the number of bytes to be returned by the target.
0x00
0xD4
R/W
WRDAT0; The 1
st
 byte to be transferred (Command Code)
0x00
0xD5
R/W
WRDAT1; 2
nd
 byte to be transferred
0x00
0xD6
R/W
WRDAT2; 3
rd
 byte to be transferred
0x00
0xD7
R/W
WRDAT3; 4
th
 byte to be transferred
0x00
0xD8
R/W
WRDAT4; 5
th
 byte to be transferred
0x00
0xD9
R/W
WRDAT5; 6th byte to be transferred
0x00
0xDA
R/W
WRDAT6; 7th byte to be transferred
0x00
0xDB
R/W
WRDAT7; 8th byte to be transferred
0x00
0xDC
R/W
WRDAT8; 9th byte to be transferred
0x00
0xDD
R/W
WRDAT9; 10th byte to be transferred
0x00
0xDE
R/W
WRDAT10; 11th byte to be transferred
0x00
0xDF
R/W
WRDAT11; 12th byte to be transferred
0x00
0xE0
R/W
WRDAT12; 13th byte to be transferred
0x00
0xE1
R/W
RDDAT0; The 1
st
 byte returned
0x00
0xE2
R/W
RDDAT1; The 2
nd
 byte returned
0x00
0xE3
R/W
RDDAT2; The 3
rd
 byte returned
0x00
0xE4
R/W
RDDAT3; The 4
th
 byte returned
0x00
0xE5
R/W
RDDAT4; The 5
th
 byte returned
0x00
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